For mixed voltage technologies, e.g. low voltage core transistors with operating voltages of about 1.8 volts to 1.2 V and high voltage input-output (I/O) transistors with operating voltages of about 3.3 volts to 2.5 volts, it is difficult to achieve both high reliability and high performance for both the core transistors and the I/O transistors without adding extra mask steps to independently optimize the core transistors and the I/O transistors.
The higher operating voltages of the I/O transistors make them susceptible to hot carrier degradation. To reduce this effect, a lightly doped drain (LDD) or drain extension is utilized. In this disclosure, LDD will be used to represent any drain extension type implant. The drain extension typically extend the heavily doped source and drain regions further under the gate of the transistor. In some applications, this LDD is formed using a low dose, high energy arsenic implant which results in acceptable reliability for the high voltage NMOS I/O transistor. In an effort to reduce masking steps, this low dose, high energy arsenic implant can also be used to form the LDD structure in the low voltage core NMOS transistor. However, this LDD structure will significantly degrade the core NMOS transistor drive current (I.sub.drive), most notably, as the drain supply voltage (VDD) for the core is scaled down from about 1.8 volts to about 1.2 volts. This drive current degradation is most probably due to the increase in the series resistance (R.sub.s R.sub.d) present in the source and drain and the associated LDD structure. As the drain supply voltage is reduced, the drive current will become increasingly limited by the this series resistance.
Thus the LDD structure required for achieving high reliability in the high voltage NMOS I/O transistors will severely degrade the I.sub.drive in the low voltage NMOS core transistors due to high series resistance R.sub.s R.sub.d and damage from the high energy arsenic implant. Present integrated circuit fabrication methodologies necessitates the use of additional masking steps to separately optimize both transistors. There is therefore great need for a reduced masking step process that will optimize both transistors and result in both high reliability and high performance without the high cost associated with increased masking steps.